FTAC 2024: 2nd Workshop on FPGA Technologies for Adaptive Computing International Conference Hall, Kyoto University Kyoto, Japan, June 4, 2024 |
Conference website | https://aitech.ac.jp/~dslab/ftac2024/ |
Submission link | https://easychair.org/conferences/?conf=ftac2024 |
Abstract registration deadline | March 31, 2024 |
Submission deadline | March 31, 2024 |
This workshop aims to discuss novel ideas and methodologies of FPGA technologies for adaptive computing. As High-Performance Computing (HPC) and Artificial Intelligence (AI) technologies become more and more important, the needs for highly efficient computing systems and architectures have also been increasing. FPGA technologies are one of the promising schemes for highly efficient adaptive computing systems, where a specific computation is done by hardware accelerators, with a much shorter time and much smaller energy consumption.
Website: https://aitech.ac.jp/~dslab/ftac2024/
Submission Guidelines
Potential authors of this workshop should prepare the extended abstract of their paper, whose length is two (2) or three (3) pages. Each submitted extended abstract will be reviewed by at least three reviewers and will be evaluated based on usefulness, originality, relevance to the workshop's theme, and technical quality.
If authors get their extended abstract accepted, they have to submit the camera-ready version of their paper that is no longer than eight (8) pages. Also, at least one of the authors has to register for the conference, and an author has to present their paper at the workshop.
To encourage discussions on innovative ideas and methodologies of early stages, the proceedings of this workshop will only provided to the workshop attendees and will NOT published.
Submission page: https://easychair.org/conferences/?conf=ftac2024
Topics of interest
- FPGA acceleration for HPC applications, such as machine learning, data engineering, scientific computation, etc.
- Innovative FPGA technologies
- Interconnection network and network-on-chip for adaptive computing
- Optimized soft processors and processing elements on FPGA
- Rapid-prototyping for FPGA-based computing engines
- Asynchronous computing circuits on FPGA
- Tools for synthesizing custom computing circuits for FPGA
- Educational systems for experiencing FPGA acceleration
Committees
Organizing committee
- General Chair: FUJIEDA, Naoki (Aichi Institute of Technology)
- Program Chair: SATO, Shimpei (Shinshu University)
Program Committee (Tentative)
- KOBAYASHI, Ryohei (University of Tsukuba)
- KISE, Kenji (Tokyo Institute of Technology)
- MIYAJIMA, Takaaki (RIKEN R-CCS)
- MIYOSHI, Takefumi (WasaLabo, LLC.)
- Nesrine Berjab (Tokyo Institute of Technology)
- OHKAWA, Takeshi (Kumamoto University)
- SAITO, Hiroshi (University of Aizu)
- TANAKA, Kiyofumi (JAIST)
- Thiem Van Chu (Tokyo Institute of Technology)
- WADA, Yasutaka (Meisei University)
Venue
June 4, 2024, International Conference Hall, Kyoto University, Kyoto, Japan
This workshop will be held in conjunction with 38th International Conference on Supercomputing (ICS 2024)
Contact
All questions about submissions should be emailed to Shimpei Sato <satos@shinshu-u.ac.jp>