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Memory Based FFT Implementation on Re-Configurable Hardware

EasyChair Preprint no. 9426

4 pagesDate: December 7, 2022


In Digital Signal Processing irrespective of Application Fast Fourier Transform (FFT) is a critical processing method while operating on discrete-time signals. The traditional way of computing FFT using a software approach by DSP processor will execute serially which restricts execution speed. The FFT implementation with optimized functionalities in parallel processing using the latest FPGA hardware is discussed in this work. In this paper, a memory-based FFT implementation on reconfigurable hardware that follows a conflict-free strategy with predefined memory size and a few other combinational components is proposed. Based on the experimental results obtained through simulations targeting ZTEX field programmable gate array (FPGA) Using Xilinx ISE, we conclude that the algorithm developed is faster than conventional approaches, with a 7.556ns delay and power consumption of 12.68 mV.

Keyphrases: Digital signal processing Re-configurable hardware ZTEX FPGA, Discrete Fourier Transform(DFT), Fast Fourier Transform (FFT), Radix-4, Xilinx ISE

BibTeX entry
BibTeX does not have the right entry for preprints. This is a hack for producing the correct reference:
  author = {Rama Krishna Thirumuru and Vani Sai Kumar Komarraju and Sai Madhava Yellamraju and Varshith Rao Gundavaram},
  title = {Memory Based FFT Implementation on Re-Configurable Hardware},
  howpublished = {EasyChair Preprint no. 9426},

  year = {EasyChair, 2022}}
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