Efficient Ternary Approximate Multiplier with Balanced Encoding Scheme and Optimized 4-2 Compressor

EasyChair Preprint no. 12304

Abstract

Approximate computing is a technique adjusting computational precision to alleviate circuit area and power consumption. This work proposes high efficiency ternary approximate multiplier in balanced ternary encoding scheme. Compared with the accurate multiplier (2-trit), the proposed multiplier shows much simpler circuit complexity with 43.5%-off in circuit area and 74.4%-off in power-delay product with only 2.25% computation error. Furthermore, optimized 4-2 compressor is proposed for the high bitwidth Wallace-tree based multiplier (6-trit). The whole design has been validated through HSPICE simulations using carbon nanotube field-effect transistors as the basic device cells. When compared with the previous works, the poroposed design shows 50.0%-off in power-delay product and 42.3%-off in circuit area, showing great potential for the future applications

Keyphrases: Approximate Computing, CNTFET, multi-valued logic, Ternary Adder, ternary logic circuits, Ternary Multiplier

@Booklet{EasyChair:12304,
  author = {Wanbo Hu and Wanting Wen and Ziye Li and Guangchao Zhao and Mingqiang Huang},
  title = {Efficient Ternary Approximate Multiplier with Balanced Encoding Scheme and Optimized 4-2 Compressor},
  howpublished = {EasyChair Preprint no. 12304},

  year = {EasyChair, 2024}}